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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:20:22 03/28/2009 
-- Design Name: 
-- Module Name:    PWMtop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
			
entity DSK_Receive_Data is
    Port ( -- data signal that we get back from DSK
				data_rx_mcbsp : in std_logic_vector (15 downto 0);
				
			  LeftPWMin : out  STD_LOGIC_VECTOR (10 downto 0);
           RightPWMin : out  STD_LOGIC_VECTOR (10 downto 0);
			  Leftin : out STD_LOGIC; --If 1 go forward else backward
			  Rightin : out STD_LOGIC; --IF 1 go forward else backward
			  
			  mclk : in  STD_LOGIC);
			  
end DSK_Receive_Data;


architecture Behavioral of DSK_Receive_Data is

begin

updateLeftandRight : process(mclk)
begin

if rising_edge(mclk) then

	if data_rx_mcbsp(15 downto 12) = X"A"	then
	LeftPWMin <= data_rx_mcbsp(11 downto 1);
	LeftIn <= data_rx_mcbsp(0);
	end if;
	
	if data_rx_mcbsp(15 downto 12) = X"B" then
	RightPWMin <= data_rx_mcbsp(11 downto 1);
	RightIn <= data_rx_mcbsp(0);
	end if;

end if;
end process;


end Behavioral;			